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SL15100
Programmable Spread Spectrum Clock Generator (SSCG)
Key Features
Low power dissipation - 7.7mA-typ at 66MHz and VDD=3.3V - 6.8mA-typ at 66MHz and VDD=2.5V Wide 2.5V to 3.3V +/-10% power supply range Programmable outputs from 3 to 200MHz Low Jitter - 110ps at 66MHz Programmable Center or Down Spread Modulation from 0.25 to 5.0% 8 to 48 MHz external crystal range 8 to 166 MHz external clock range Integrated internal voltage regulator Programmable PD#/OE/SSON#/FS functions Programmable CL at XIN and XOUT pins Programmable output rise and fall times Programmable modulation frequency from 30 to 120 kHz
Description
The SL15100 a programmable low power Spread Spectrum Clock Generator (SSCG) used for reducing Electromagnetic Interference (EMI). The product is designed using SpectraLinear proprietary EProClockTM programmable phase-locked loop (PLL) and Spread Spectrum Clock (SSC) technology to synthesize and modulate the input clock. The modulated clock can significantly reduce the measured EMI levels, and leading to the compliance with regulatory agency requirements. The output clock frequency, Spread %, output rise and fall times, crystal load, modulation frequency and PD#/OE/SSON#/FS functions can be programmed to meet the needs of wide range of applications. The SL15100 operates from 2.5V to 3.3V power supply voltage range. The product is offered in 8-pin TSSOP package with commercial and industrial grades. Refer to SL15101 for up to four (4) programmable clock outputs and SL15L100/101 Programmable SSCG products for 1.8V power supply operation.
Applications
Printers, MFPs Digital Copiers NBPCs and LCD Monitors Routers, Servers and Switchers HDTV and DVD-R/W
Benefits
Peak EMI reduction of 8 to 16 dB Fast time-to-market Cost Reduction Reduction of PCB layers Eleminates the need for higher order crystals (Xtals) and crystal oscillators (XOs)
Block Diagram
Rev 1.8, August 10, 2007
Page 1 of 16
2200 Laurelwood Road, Santa Clara, CA 95054 Tel: (408) 855-0555 Fax: (408) 855-0550 www.SpectraLinear.com
SL15100
Pin Configuration
8-Pin TSSOP
Pin Description
Pin Number
1 2 3 4
Pin Name
VDD XOUT XIN/CLKIN PD#/OE
Pin Type
Power Output Input Input Positive power supply.
Pin Description
Crystal or ceramic resonator output pin. Leave this pin unconnected (floating) if external clock is used at Pin-3. Crystal, ceramic resonator or external clock input pin. User Programmable PD# or OE control pin. Power Down (PD#-Active Low): If PD#=0(Low), the device is powered down and both SSCLK and REFOUT outputs are weakly pulled low to VSS. Output Enable (OEActive High): If OE=1(High), the SSCLK and REFOUT outputs are enabled. PD# or OE is weakly pulled high to VDD.
5 6 7 8
VSS SSCLK1 or REFCLK1 SSCLK2 or REFCLK2 SSON#/FS
Power Output Output Input
Power supply ground. This pin can be programmed as SSCLK1 or REFCLK1. This pin can be programmed as SSCLK2 or REFCLK2. Programmable SSON# or Frequency Select (FS) Control pin. If SSCG# function is programmed: Spread-on=0(Low) or Spread-off=1(High). If FS function is programmed: The clock frequencies can be switched between two sets of frequencies as programmed. SSON# or FS is weakly pulled low to VSS.
Rev 1.8, August 10, 2007
Page 2 of 16
SL15100
General Description The primary source of EMI from digital circuits is the system clock and all the other synchronous clocks and control signals derived from the system clock. The well know techniques of filtering (suppression) and shielding (containment), while effective, can cost money, board space and longer development time. A more effective and efficient technique to reduce EMI is Spread Spectrum Clock Generator (SSCG) technique. Instead of using constant clock frequency, the SSCG technique modulates (spreads) the system clock with a much smaller frequency, to reduce EMI emissions at its source: The System Clock. The SL15100 is designed using SpectraLinear proprietary programmable EProClockTM phase-locked loop (PLL) and Spread Spectrum Technologies (SST) to synthesize and modulate (spread) the system clock such that the energy is spread out over a wider bandwidth. This reduces the peak value of the radiated emissions at the fundamental and the harmonics. This reduction in radiated energy can significantly reduce the cost of complying with regulatory agency requirements and improve time-to-market without degrading system performance. The SL15100 operates with both 3.3V and 2.5V power supply voltages. Refer to SL15L100 for 1.8V power supply operation. The SL15100 is available in 8-pin TSSOP package with Extended Commercial Temperature range of 0 to +85 C and Industrial Temperature range of -40 to +85C. Input Frequency Range The input frequency range is from 8.0 to 48.0 MHz for crystals and ceramic resonators. If an external clock is used, the input frequency range is from 8 to 166 MHz. Output Frequency Range and Outputs The two (2) outputs can be programmed as SSCLK or REFCLK. SSCLK output can be synthesized to any value from 3 to 200 MHz with spread based on valid input frequency. The spread at SSCLK pins can be stopped by SSON# input control pin, If SSON# pin is HIGH (VDD), the frequency at this pin is the synthesized nominal value of the input frequency and there is no spread. REFOUT is the buffered output of the oscillator and is the same frequency as the input frequency without spread. However, REFOUT value can also be divided by using the output dividers from 2 to 32. The second programmable output (SSCLK2) can be used to generate a copy of SSCLK1 (fanout of 2) or the same SSCLK frequency can be divided from 2 to 32. In this case, the spread % value is the same as the original programmed spread % value. By using only first order crystals, SL15100 can synthesize output frequency up to 200 MHz, eliminating the need for higher order Crystals (Xtals) and Crystal Oscillators (XOs). This reduces the cost while improving the system clock accuracy, performance and reliability.
Rev 1.8, August 10, 2007
Programmable CL (Crystal Load) The SL15100 provides programmable on-chip capacitors at XIN/CLKIN (Pin-3) and XOUT (Pin-2). The resolution of this programmable capacitor is 6-bits with LSB value of 0.5pF. When all bits are off the pin capacitance is CXIN=CXOUT =8.5pF (minimum value). When all bits are on the pin capacitance is CXIN=CXOUT=40pF (maximum value). The values of CXIN and CXOUT based on the CL (Crystal Load Capacitor) can be calculated as: CXIN=CXOUT=2CL-CPCB. Refer to the Page-13 for additional information on crystal load (CL). In addition, if an external clock is used, the capacitance at Pin-3 (CLKIN) can programmed to control the edge rate of this input clock, providing additional EMI control. Programmable Modulation Frequency The Spread Spectrum Clock (SSC) modulation default value is 31.5 kHz. The higher value of up to120 kHz can also be programmed. Less than 30 kHz modulation frequency is not recommended to stay out of the range audio frequency bandwidth since this frequency could be detected as a noise by the audio receivers within the vicinity. Programmable Spread Percent (%) The spread percent (%) value is programmable from +/0.25% to +/-2.5% (center spread) or -0.5% to -5.0% (down spread) for all SSCLK frequencies. It is possible to program smaller or larger non-standard values of spread percent. Contact SLI if these non-standard spread percent values are required in the application. SSON# or Frequency Select (FS) The SL15100 Pin-8 can be programmed as either SSON# to enable or disable the programmed spread percent value or as Frequency Select (FS). If SSON# is used, when this pin is pulled high (VDD), the spread is stopped and the frequency is the nominal value without spread. If low (GND), the frequency is the nominal value with the spread. If FS function is used, the output pins can be programmed for different set of frequencies as selected by FS. SSCLK value can be any frequency from 3 to 200MHz, but the spread % is the same percent value. REFOUT is the same frequency as the input reference clock or divide by from 2 to 32 without spread. The set of frequencies in Table 1 is given as en example, using 48MHz crystal. The SL15100 also allows a fan-out of 2, meaning that Pins 6 and 7 can be programmed to the same frequencies with or without spread such that F1=F2 and F3=F4.
FS (Pin-8) 0 1 SSCLK1 (Pin-6) F1= 66MHz, +/-1% F3 =125MHz,+/-3% REFCLK2 (Pin-7) F2= 48MHz F4= 24MHz
Table 1. Frequency Selection (FS) Power Down (PD#) or Output Enable (OE) The SL15100 Pin-4 can be programmed as either PD# or OE. PD# powers down the entire chip whereas OE only disables the output buffers to Hi-Z.
Page 3 of 16
SL15100
Absolute Maximum Ratings
Description Supply voltage, VDD All Inputs and Outputs Ambient Operating Temperature Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature ESD Rating (Human Body Model) ESD Rating (Charge Device Model) ESD Rating (Machine Model) Latch-up JEDEC22-A114D JEDEC22-C101C JEDEC22-A115D 125C In operation, C-Grade In operation, I-Grade No power is applied In operation, power is applied Condition Min -0.5 -0.5 0 -40 -65 -4,000 -1,500 -250 -200 Max 4.6 VDD+0.5 85 85 150 125 260 4,000 1,500 250 200 Unit V V C C C C C V V V mA
DC Electrical Characteristics (C-Grade)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +85 Deg C
Description
Operating Voltage Input Low Voltage Input High Voltage Output High Voltage Output Low Voltage Input High Current Input Low Current
Symbol
VDD VIL VIH VOH1 VOL1 IIH IIL
Condition
VDD+/-10% CMOS Level, Pins 4 and 8 CMOS Level, Pins 4 and 8 IOH=10mA , Pins 6 and 7 IOL=10mA, Pins 6 and 7 VIN=VDD, Pins 4 and 8 If no pull-up/down resister used VIN=GND, Pins 4 and 8 If no pull-up/down resister used FIN=30MHz, REFCLK=30MHz SSCLK=66MHz, PD#/OE=VDD SSON#=GND, CL=0 PD#=GND Pins 6 and 7 Minimum setting value
Min
2.97 0 0.7VDD VDD-0.5 -
Typ
3.3 -
Max
3.63 0.3VDD VDD 0.5 10 10
Unit
V V V V V A A
Operating Supply Current Standby Current Output Leakage Current Programmable Input Capacitance at Pins 2 and 3 Input Capacitance Load Capacitance
IDD ISBC IOL PCin PCout CIN2 CL
-10 -
7.7 70 8.5 40 0.5 4 -
9.2 90 10 6 15
mA A A pF pF pF pF pF
Maximum setting value Resolution (programming steps) Pins 4 and 8 SSCLK/REFCLK , Pins 6 and 7
Rev 1.8, August 10, 2007
Page 4 of 16
SL15100
AC Electrical Characteristics (C-Grade)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +85 Deg C
Parameter
Input Frequency Range Input Frequency Range
Symbol
FIN1 FIN2
Condition
Crystal or Ceramic Resonator External Clock SSCLK REFCLK, crystal or resonator input REFCLK, clock input SSCLK REFCLK Clock Input, Pin 3 Programmable, VDD=3.3 CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3 CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3 CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3 CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3 CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3 CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3 CL=15pF, 20 to 80% of VDD CLKIN=SSCLK=166MHz, 2%Spread REFCLK=Off CLKIN=SSCLK=66MHz, 2%Spread REFCLK=Off CLKIN=SSCLK=33MHz, 2%Spread REFCLK=Off CLKIN=SSCLK=166MHz, 2%Spread REFCLK=On CLKIN=SSCLK=66MHz, 2%Spread REFCLK=On CLKIN=SSCLK=33MHz, 2%Spread REFCLK=On CLKIN=SSCLK=166MHz, 2%Spread REFCLK=On
Min
8 8 3 0.25 0.25 45 45 40 -
Typ
50 50 50 4.00 2.00 1.40 1.10 0.85 0.70 0.55 90 100 120 100 105 180 80
Max
48 166 200 48 166 55 55 60 4.80 2.40 1.70 1.35 1.00 0.85 0.67 120 130 160 130 140 240 100
Unit
MHz MHz MHz MHz MHz % % % ns ns ns ns ns ns ns ps ps ps ps ps ps ps
Output Frequency Range FOUT1 Output Frequency Range FOUT2 Output Frequency Range FOUT3 Output Duty Cycle Output Duty Cycle Input Duty Cycle Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Cycle-to-Cycle Jitter (SSCLK - Pin 7) Cycle-to-Cycle Jitter (SSCLK - Pin 7) Cycle-to-Cycle Jitter (SSCLK - Pin 7) Cycle-to-Cycle Jitter (SSCLK - Pin 7) Cycle-to-Cycle Jitter (SSCLK - Pin 7) Cycle-to-Cycle Jitter (SSCLK - Pin 7) Cycle-to-Cycle Jitter (SSCLK - Pin 6) DC1 DC2 DCIN tr/f1 tr/f2 tr/f3 tr/f4 tr/f5 tr/f6 tr/f7 CCJ1 CCJ2 CCJ3 CCJ4 CCJ5 CCJ6 CCJ7
Rev 1.8, August 10, 2007
Page 5 of 16
SL15100
Cycle-to-Cycle Jitter (SSCLK - Pin 6) Cycle-to-Cycle Jitter (SSCLK - Pin 6) Power-down Time Power-up Time (Crystal or Resonator) Power-up Time (Clock) Output Enable Time Output Disable Time Spread Percent Range Spread Percent Variation Modulation Frequency CCJ8 CCJ9 tPD tPU1 tPU2 tOE tOD SPR SS% FMOD CLKIN=SSCLK=66MHz, 2%Spread REFCLK=On CLKIN=SSCLK=33MHz, 2%Spread REFCLK=On Time from PD# falling edge to Hi-Z at outputs (Asynchronous) Time from PD# rising edge to valid frequency at outputs (Asynchronous) Time from PD# rising edge to valid frequency at outputs (Asynchronous) Time from OE falling edge to Hi-Z at outputs (Asynchronous) Time from OE falling edge to Hi-Z at outputs (Asynchronous) SSCLK-1/2 Outputs Variation of programmed Spread % Programmable, 31.5 kHz standard 0.25 -15 30 100 135 150 3.5 2.0 180 180 31.5 130 180 350 5.0 3.0 350 350 5.0 15 120 ps ps ns ms ms ns ns % % kHz
DC Electrical Characteristics (C-Grade)
Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range 0 to +85 Deg C
Description
Operating Voltage Input Low Voltage Input High Voltage Output High Voltage Output Low Voltage Input High Current Input Low Current Pull-up/Down Resistors Operating Supply Current Standby Current Output Leakage Current Programmable Input Capacitance at Pins 2 and 3
Symbol
VDD VIL VIH VOH1 VOL1 IIH IIL RPU/D IDD ISBC IOL CXIN CXOUT
Condition
VDD+/-10% CMOS Level, Pins 4 and 8 CMOS Level, Pins 4 and 8 IOH=6mA , Pins 6 and 7 IOL=6mA, Pins 6 and 7 VIN=VDD, Pins 4 and 8 If no pull-up/down resister used VIN=GND, Pins 4 and 8 If no pull-up/down resister used VIN=VDD or GND FIN=30MHz, REFCLK=30MHz SSCLK=66MHz, PD#/OE=VDD SSON#=GND, CL=0 PD#=GND Pins 6 and 7 Minimum programming value Maximum programming value Resolution (programming steps)
Min
2.25 0 0.7VDD VDD-0.5 90 -10 -
Typ
2.5 160 6.8 70 8.5 40 0.5
Max
2.75 0.3VDD VDD 0.5 10 10 230 8.1 90 10 -
Unit
V V V V V A A k mA A A pF pF pF
Rev 1.8, August 10, 2007
Page 6 of 16
SL15100
Input Capacitance Load Capacitance CIN2 CL Pins 4 and 8 SSCLK/REFCLK , Pins 6 and 7 4 6 15 pF pF
AC Electrical Characteristics (C-Grade)
Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range 0 to +85 Deg C
Parameter
Input Frequency Range Input Frequency Range
Symbol
FIN1 FIN2
Condition
Crystal or Ceramic Resonator External Clock SSCLK REFCLK, crystal or resonator input REFCLK, clock input SSCLK REFCLK Clock Input, Pin 3 Programmable, VDD=2.5 CL=15pF, 20 to 80% of VDD Programmable, VDD=2.5 CL=15pF, 20 to 80% of VDD Programmable, VDD=2.5 CL=15pF, 20 to 80% of VDD Programmable, VDD=2.5 CL=15pF, 20 to 80% of VDD Programmable, VDD=2.5 CL=15pF, 20 to 80% of VDD Programmable, VDD=2.5 CL=15pF, 20 to 80% of VDD Programmable, VDD=2.5 CL=15pF, 20 to 80% of VDD CLKIN=SSCLK=166MHz, 2%Spread REFCLK=Off CLKIN=SSCLK=66MHz, 2%Spread, REFCLK=Off CLKIN=SSCLK=33MHz, 2%Spread, REFCLK=Off CLKIN=SSCLK=166MHz, 2%Spread REFCLK=On CLKIN=SSCLK=66MHz, 2%Spread, REFCLK=On
Min
8 8 3 0.25 0.25 45 45 40 -
Typ
50 50 50 4.80 2.60 1.80 1.40 1.10 0.90 0.70 100
Max
48 166 200 48 166 55 55 60 5.80 3.10 2.20 1.70 1.35 1.10 0.85 130
Unit
MHz MHz MHz MHz MHz % % % ns ns ns ns ns ns ns ps
Output Frequency Range FOUT1 Output Frequency Range FOUT2 Output Frequency Range FOUT3 Output Duty Cycle Output Duty Cycle Input Duty Cycle Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Cycle-to-Cycle Jitter (SSCLK - Pin 7) Cycle-to-Cycle Jitter (SSCLK - Pin 7) Cycle-to-Cycle Jitter (SSCLK - Pin 7) Cycle-to-Cycle Jitter (SSCLK - Pin 7) Cycle-to-Cycle Jitter (SSCLK - Pin 7) DC1 DC2 DCIN tr/f1 tr/f2 tr/f3 tr/f4 tr/f5 tr/f6 tr/f7 CCJ1
CCJ2 CCJ3 CCJ4 CCJ5
-
110 130 110 115
140 170 140 150
ps ps ps ps
Rev 1.8, August 10, 2007
Page 7 of 16
SL15100
Cycle-to-Cycle Jitter (SSCLK - Pin 7) Cycle-to-Cycle Jitter (SSCLK - Pin 6) Cycle-to-Cycle Jitter (SSCLK - Pin 6) Cycle-to-Cycle Jitter (SSCLK - Pin 6) Power-down Time Power-up Time (Crystal or Resonator) Power-up Time (Clock) Output Enable Time Output Disable Time Spread Percent Range Spread Percent Variation Modulation Frequency CCJ6 CCJ7 CCJ8 CCJ9 tPD tPU1 CLKIN=SSCLK=33MHz, 2%Spread, REFCLK=On CLKIN=SSCLK=166MHz, 2%Spread, REFCLK=On CLKIN=SSCLK=66MHz, 2%Spread REFCLK=On CLKIN=SSCLK=33MHz, 2%Spread REFCLK=On Time from PD# falling edge to Hi-Z at outputs (Asynchronous) Time from PD# rising edge to valid frequency at outputs (Asynchronous) Time from PD# rising edge to valid frequency at outputs (Asynchronous) Time from OE falling edge to Hi-Z at outputs (Asynchronous) Time from OE falling edge to Hi-Z at outputs (Asynchronous) SSCLK-1/2 Variation of programmed Spread % Programmable, 31.5 kHz standard 200 90 110 150 180 3.5 260 110 140 200 350 5.0 ps ps ps ps ns ms
tPU2
-
2.0
3.0
ms
tOE tOD SPR SS% FMOD
0.25 -15 30
180 180 31.5
350 350 5.0 15 120
ns ns % % kHz
DC Electrical Characteristics (I-Grade)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85 Deg C
Description
Operating Voltage Input Low Voltage Input High Voltage Output High Voltage Output Low Voltage Input High Current Input Low Current
Symbol
VDD VIL VIH VOH1 VOL1 IIH IIL
Condition
VDD+/-10% CMOS Level, Pins 4 and 8 CMOS Level, Pins 4 and 8 IOH=8mA , Pins 6 and 7 IOL=8mA, Pins 6 and 7 VIN=VDD, Pins 4 and 8 If no pull-up/down resister used VIN=GND, Pins 4 and 8 If no pull-up/down resister used VIN=VDD or GND FIN=30MHz, REFCLK=30MHz SSCLK=66MHz, PD#/OE=VDD SSON#=GND, CL=0
Min
2.97 0 0.7VDD VDD-0.5 100 -
Typ
3.3 160 8.0
Max
3.63 0.3VDD VDD 0.5 15 15 220 9.6
Unit
V V V V V A A k mA
Pull-up or Down Resistor RPU/D Operating Supply Current IDD
Rev 1.8, August 10, 2007
Page 8 of 16
SL15100
Standby Current Output Leakage Current Programmable Input Capacitance at Pins 2 and 3 Input Capacitance Load Capacitance ISBC IOL CXIN CXOUT CIN2 CL PD#=GND Pins 6 and 7 Minimum setting value Maximum setting value Resolution (programming steps) Pins 4 and 8 SSCLK/REFCLK , Pins 6 and 7 -15 80 8.5 40 0.5 4 100 15 7 15 A A pF pF pF pF pF
AC Electrical Characteristics (I-Grade)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85 Deg C
Parameter
Input Frequency Range Input Frequency Range
Symbol
FIN1 FIN2
Condition
Crystal or Ceramic Resonator External Clock SSCLK REFCLK, crystal or resonator input REFCLK, clock input SSCLK REFCLK Clock Input, Pin 3 Programmable, VDD=3.3 CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3 CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3 CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3 CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3 CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3 CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3 CL=15pF, 20 to 80% of VDD CLKIN=SSCLK=166MHz, 2%Spread REFCLK=Off CLKIN=SSCLK=66MHz, 2%Spread REFCLK=Off CLKIN=SSCLK=33MHz, 2%Spread
Min
8 8 3 0.25 0.25 45 45 40 -
Typ
50 50 50 4.00 2.00 1.40 1.10 0.85 0.70 0.55 100 110 130
Max
48 166 200 48 166 55 55 60 4.80 2.40 1.70 1.35 1.00 0.85 0.67 135 145 175
Unit
MHz MHz MHz MHz MHz % % % ns ns ns ns ns ns ns ps ps ps
Output Frequency Range FOUT1 Output Frequency Range FOUT2 Output Frequency Range FOUT3 Output Duty Cycle Output Duty Cycle Input Duty Cycle Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Cycle-to-Cycle Jitter (SSCLK - Pin 7) Cycle-to-Cycle Jitter (SSCLK - Pin 7) Cycle-to-Cycle Jitter DC1 DC2 DCIN tr/f1 tr/f2 tr/f3 tr/f4 tr/f5 tr/f6 tr/f7 CCJ1 CCJ2 CCJ3
Rev 1.8, August 10, 2007
Page 9 of 16
SL15100
(SSCLK - Pin 7) Cycle-to-Cycle Jitter (SSCLK - Pin 7) Cycle-to-Cycle Jitter (SSCLK - Pin 7) Cycle-to-Cycle Jitter (SSCLK - Pin 7) Cycle-to-Cycle Jitter (SSCLK - Pin 6) Cycle-to-Cycle Jitter (SSCLK - Pin 6) Cycle-to-Cycle Jitter (SSCLK - Pin 6) Power-down Time Power-up Time (Crystal or Resonator) Power-up Time (Clock) Output Enable Time Output Disable Time Spread Percent Range Spread Percent Variation Modulation Frequency CCJ4 CCJ5 CCJ6 CCJ7 CCJ8 CCJ9 tPD tPU1 tPU2 tOE tOD SPR SS% FMOD REFCLK=Off CLKIN=SSCLK=166MHz, 2%Spread REFCLK=On CLKIN=SSCLK=66MHz, 2%Spread REFCLK=On CLKIN=SSCLK=33MHz, 2%Spread REFCLK=On CLKIN=SSCLK=166MHz, 2%Spread REFCLK=On CLKIN=SSCLK=66MHz, 2%Spread REFCLK=On CLKIN=SSCLK=33MHz, 2%Spread REFCLK=On Time from PD# falling edge to Hi-Z at outputs (Asynchronous) Time from PD# rising edge to valid frequency at outputs (Asynchronous) Time from PD# rising edge to valid frequency at outputs (Asynchronous) Time from OE falling edge to Hi-Z at outputs (Asynchronous) Time from OE falling edge to Hi-Z at outputs (Asynchronous) SSCLK-1/2 Variation of programmed Spread % Programmable, 31.5 kHz standard 0.25 -20 30 110 115 190 90 110 145 150 3.5 2.0 150 150 31.5 145 155 255 115 145 195 350 5.0 3.0 350 350 5.0 20 120 ps ps ps ps ps ps ns ms ms ns ns % % kHz
DC Electrical Characteristics (I-Grade)
Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85 Deg C
Description
Operating Voltage Input Low Voltage Input High Voltage Output High Voltage Output Low Voltage Input High Current Input Low Current Pull-up or Down Resistors
Symbol
VDD VIL VIH VOH1 VOL1 IIH IIL RPU/D
Condition
VDD+/-10% CMOS Level, Pins 4 and 8 CMOS Level, Pins 4 and 8 IOH=6mA , Pins 6 and 7 IOL=6mA, Pins 6 and 7 VIN=VDD, Pins 4 and 8 If no pull-up/down resister used VIN=GND, Pins 4 and 8 If no pull-up/down resister used Vin=VDD or GND
Min
2.25 0 0.7VDD VDD-0.4 90
Typ
2.5 160
Max
2.75 0.3VDD VDD 0.4 15 15 230
Unit
V V V V V A A k
Rev 1.8, August 10, 2007
Page 10 of 16
SL15100
Operating Supply Current Standby Current Output Leakage Current Programmable Input Capacitance at Pins 2 and 3 Input Capacitance Load Capacitance IDD ISBC IOL CXIN CXOUT CIN2 CL FIN=30MHz, REFCLK=30MHz SSCLK=66MHz, PD#/OE=VDD SSON#=GND, CL=0 PD#=GND Pins 6 and 7 Minimum setting value Maximum setting value Resolution (programming steps) Pins 4 and 8 SSCLK/REFCLK , Pins 6 and 7 -10 7.0 80 8.5 40 0.5 4 8.4 100 10 7 15 mA A A pF pF pF pF pF
AC Electrical Characteristics (I-Grade)
Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85 Deg C
Parameter
Input Frequency Range Input Frequency Range
Symbol
FIN1 FIN2
Condition
Crystal or Ceramic Resonator External Clock SSCLK REFCLK, crystal or resonator input REFCLK, clock input SSCLK REFCLK Clock Input, Pin 3 Programmable, VDD=2.5 CL=15pF, 20 to 80% of VDD Programmable, VDD=2.5 CL=15pF, 20 to 80% of VDD Programmable, VDD=2.5 CL=15pF, 20 to 80% of VDD Programmable, VDD=2.5 CL=15pF, 20 to 80% of VDD Programmable, VDD=2.5 CL=15pF, 20 to 80% of VDD Programmable, VDD=2.5 CL=15pF, 20 to 80% of VDD Programmable, VDD=2.5 CL=15pF, 20 to 80% of VDD CLKIN=SSCLK=166MHz, 2%Spread REFCLK=Off
Min
8 8 3 0.25 0.25 45 45 40 -
Typ
50 50 50 4.80 2.60 1.80 1.40 1.10 0.90 0.70 115
Max
48 166 200 48 166 55 55 60 5.80 3.10 2.20 1.70 1.35 1.10 0.85 150
Unit
MHz MHz MHz MHz MHz % % % ns ns ns ns ns ns ns ps
Output Frequency Range FOUT1 Output Frequency Range FOUT2 Output Frequency Range FOUT3 Output Duty Cycle Output Duty Cycle Input Duty Cycle Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Cycle-to-Cycle Jitter (SSCLK - Pin 7) DC1 DC2 DCIN tr/f1 tr/f2 tr/f3 tr/f4 tr/f5 tr/f6 tr/f7 CCJ1
Rev 1.8, August 10, 2007
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SL15100
Cycle-to-Cycle Jitter (SSCLK - Pin 7) Cycle-to-Cycle Jitter (SSCLK - Pin 7) Cycle-to-Cycle Jitter (SSCLK - Pin 7) Cycle-to-Cycle Jitter (SSCLK - Pin 7) Cycle-to-Cycle Jitter (SSCLK - Pin 7) Cycle-to-Cycle Jitter (SSCLK - Pin 6) Cycle-to-Cycle Jitter (SSCLK - Pin 6) Cycle-to-Cycle Jitter (SSCLK - Pin 6) Power-down Time Power-up Time (Crystal or Resonator) Power-up Time (Clock) Output Enable Time Output Disable Time Spread Percent Range Spread Percent Variation Modulation Frequency CCJ2 CCJ3 CCJ4 CCJ5 CCJ6 CCJ7 CCJ8 CCJ9 tPD tPU1 tPU2 tOE tOD SPR SS% FMOD CLKIN=SSCLK=66MHz, 2%Spread REFCLK=Off CLKIN=SSCLK=33MHz, 2%Spread REFCLK=Off CLKIN=SSCLK=166MHz, 2%Spread REFCLK=On CLKIN=SSCLK=66MHz, 2%Spread REFCLK=On CLKIN=SSCLK=33MHz, 2%Spread REFCLK=On CLKIN=SSCLK=166MHz, 2%Spread REFCLK=On CLKIN=SSCLK=66MHz, 2%Spread REFCLK=On CLKIN=SSCLK=33MHz, 2%Spread REFCLK=On Time from PD# falling edge to Hi-Z at outputs (Asynchronous) Time from PD# rising edge to valid frequency at outputs (Asynchronous) Time from PD# rising edge to valid frequency at outputs (Asynchronous) Time from OE falling edge to Hi-Z at outputs (Asynchronous) Time from OE falling edge to Hi-Z at outputs (Asynchronous) SSCLK-1/2 Variation of programmed Spread % Programmable, 31.5 kHz standard 0.25 -20 30 125 125 145 125 215 105 125 165 180 3.5 2.0 180 180 31.5 160 160 185 160 280 130 160 220 350 5.0 3.0 350 350 5.0 20 120 ps ps ps ps ps ps ps ps ns ms ms ns ns % % kHz
Rev 1.8, August 10, 2007
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SL15100
External Components & Design Considerations
Typical Application Schematic
Comments and Recommendations
Decoupling Capacitor: A decoupling capacitor of 0.1 F must be used between VDD and VSS on the pins 1 and 5. Place the capacitor on the component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin and to the GND via should be kept as short as possible Do not use vias between the decoupling capacitor and the VDD pin. Series Termination Resistor: A series termination resistor is recommended if the distance between the output (SSCLK) and the load is over 1 1/2 inch. The nominal impedance of the SSCLK output is about 30 . Use 20 resistor in series with the output to terminate 50 trace impedance and place 20 resistor as close to the SSCLK output as possible. Crystal and Crystal Load: Use only parallel resonant fundamental crystals. DO NOT USE higher overtone crystals. To meet the crystal initial accuracy specification (in ppm); the internal on-chip programmable capacitors PCin and PCout must be programmed to match the crystal load requirement. These values are given by the formula below: PCin(pF) =PCout(pF)= [(CL(pF) - Cp(pF)/2)] x 2 Where CL is crystal load capacitor as given by the crystal datasheet and Cp(pF) is the compensation factor for the total parasitic capacitance at XIN or XOUT pin including PCB related parasitic capacitance. As an example; if a crystal with CL=18pF is used and Cp=4pF, by using the above formula, PCin=PCout=[(18-(4/2)] x 2 = 32pF. Programming PCin and PCout to 32pF assures that this crystal sees an equivalent load of 18pF and no other external crystal load capacitor is needed. Deviating from the crystal load specification could cause an increase in frequency accuracy in ppm. Refer to the Table 5 for the recommended crystal specifications.
Rev 1.8, August 10, 2007
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SL15100
Recommended External Crystal Specifications
Parameter FNOM CL R1,1 R1,2 R1,3 DL1,1 DL1,2 Co1 Co2
Description Nominal Crystal Frequency Range Nominal Crystal Load Equivalent Series Resistance Equivalent Series Resistance Equivalent Series Resistance Crystal Drive Level Crystal Drive Level Shunt Capacitance Shunt Capacitance
Min 8 6 20 12.5 10 -
Typ 12 40 25 20 4 5
Max 48 18 100 60 50 200 150 5.4 7.2
Unit MHz pF Ohm Ohm Ohm W W pF pF
Comments Fundamental Mode - AT Cut Load for +/-0 ppm Fo resonance value F-Range: 8.0 to 12.999 MHz F-Range: 13.0 to 19.999 MHz F-Range: 20.0 to 48.000 MHz F-Range: 8.0 to 19.999 MHz F-Range: 20.0 to 48.000 MHz SMD Xtals Through Hole (Leaded) Xtals
Table 5. Recommended Crystal Specifications
Rev 1.8, August 10, 2007
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SL15100
Package Outline and Package Dimensions 8-Pin TSSOP Package (173 Mil)
Thermal Characteristics
Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Symbol
JA1 JA2 JA3 JC
Condition Still air 1m/s air flow 3m/s air flow Independent of air flow
Min -
Typ 110 100 80 35
Max -
Unit C/W C/W C/W C/W
Rev 1.8, August 10, 2007
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SL15100
Ordering Information [1]
Ordering Number
[2]
Marking TBD TBD TBD TBD
Shipping Package Tube Tape and Reel Tube Tape and Reel
Package 8-pin TSSOP 8-pin TSSOP 8-pin TSSOP 8-pin TSSOP
Temperature 0 to 85C 0 to 85C -40 to 85C -40 to 85C
SL15100ZC-XXX SL15100ZCT-XXX SL15100ZI-XXX SL15100ZIT-XXX
Notes: 1. All SLI products are RoHS compliant. 2. "XXX" is "Dash" number and will be assigned by SLI for the final programmed samples or production the units based on the each customer programming requirements.
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted not is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and an expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice.
Rev 1.8, August 10, 2007
Page 16 of 16

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